← Back

ASIC Engineering Digital Designer/ Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 8-12 Years | Pune)

Cisco · Pune, IN, India

Cisco is hiring a lead ASIC Engineering Digital Designer/ Leader ( digital design, FSM, CPU sub-systems, complex SOCs, FPGA validation | 8-12 Years | Pune) in Pune, IN, India. What you'll do: prototyping and testing / qa, work across the infrastructure and security domains.
Occupation classification pending for this posting — SOC-level hiring signals will appear here once the classifier tags it.
Category
Backend
Source
careers.cisco.com
Original link
https://careers.cisco.com/global/en/job/CISCISGLOBAL2013154EXTERNALENGLOBAL/ASIC-Engineering-Digital-Designer-Leader-digital-design-FSM-CPU-sub-systems-complex-SOCs-FPGA-validation-8-12-Years-Pune
Posted
2 weeks ago (2026-05-21)
Status
active

Topics: Infrastructure, Security

Activities: Prototyping, Testing / QA

Community signals

No approved reports yet.

Add your experience

Share a factual experience about timing or process. Avoid accusations, personal information, or legal claims. New reports are held for moderation.

Tags

Please report your experience respectfully. Notes containing profanity, slurs, personal attacks, or slanderous claims will be automatically removed. Describe what happened — timelines, communication, outcomes — not how you feel about the people involved.

Approved reports

No approved reports yet.

Stay in the loop

Get the occasional update on job-market trends, ghost-job patterns, and what we’re shipping. No spam.